1. Field of the Invention
This invention relates in general to memory and more specifically to memory cells with lower power consumption during a write operation.
2. Description of the Related Art
Increasingly, low voltage and low power memory cells are being used in static random access memories (SRAMs) for use in portable applications. Further, portable applications are also requiring larger SRAM cache sizes. With the dual requirements of lower voltages and increased cache sizes, read and write stability of six transistors (6T) memory cells is difficult to maintain. To alleviate these issues, some implementations of SRAM are based on eight transistor (8T) memory cells.
Although such eight transistor (8T) memory cells have certain advantages, they are not suited for high-density SRAM designs, since they occupy more space than 6T memory cells. Furthermore, 8T cells are not suited for low power technology because of higher power consumption. In some instances, row-biasing is used to lower the power consumption of such 8T cells during a write operation. However, when row-biasing is implemented in such 8T cells, it further increases the memory cell size. This in turn, makes these 8T cells further unsuitable for high-density SRAM designs.
Thus, there is a need for memory cells with lower power consumption during a write operation.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.